1. Field of the Invention
The present invention relates to wireless communication systems, such as but not limited to wireless local area networks (WLANs), and in particular, to an 802.11b Complementary Code Keying (CCK) receiver which mitigates inter-symbol and intra-symbol distortions due to multipath propagation.
2. Description of the Prior Art
U.S. Patent Application Publication No. 2001/0036223 to Webster et al.(“Webster”) discloses a RAKE receiver that is used for indoor multipath WLAN applications on direct spread spectrum signals having relatively short codeword lengths. FIGS. 6, 7, 8, and 10 of Webster illustrate a RAKE receiver which has an embedded chip-based decision feedback equalizer (DFE) structure provided in the signal processing path between the receiver's channel matched filter (CMF) and codeword correlator. The DFE serves to cancel Inter-Symbol Interference (ISI), which is also known as inter-codeword interference (i.e., bleed-over between CCK codewords), of the previous CCK codeword.
FIGS. 12–14 of Webster illustrate an Intra-Symbol Chip Interference (ICI) canceller which is designed to cancel the ICI generated from the post-cursors through the use of lengthy complex operations (multiplications and additions), and includes one DFE convolution block and one codeword correlation block for each and every codeword (up to 256 codewords in total) in a 802.11b CCK Decoder. Each of the 64 or 256 ICI outputs is calculated independently from a separate processing path.
In FIG. 12 of Webster, for each and every codeword (256 codewords in total), three basic building blocks are required: (i) one DFE convolution block 1220 which calculates chip-by-chip representation of the ICI before the codeword correlator 1230 using the complex convolution between each codeword (8 complex chips denoted as OW#k CHIP) and up to 8 complex DFE taps, (ii) one chip-by-chip subtractor 1210 which subtracts each of the 8 received complex chips (block 1203) from the outputs of block 1220, and (iii) one codeword correlator 1230 which calculates the correlation between each codeword (8 complex chips) and the results (8 complex chips) from the subtractor 1210. All these operations are complex and are required for each codeword. In short, 256 ICI bias outputs 1212 are calculated independently at blocks 1220, subtracted in parallel at blocks 1210, and then 256 correlations outputs are found from the codeword correlators 1230. Because the input 1223 to each codeword correlator 1230 is now different after the ICI bias correction, this architecture prevents the use of a fast Walsh transform implementation to jointly and effectively calculate the CCK correlations for all CCK codewords.
In another embodiment illustrated in FIG. 13 of Webster, for each and every codeword (64 codewords in total), two basic building blocks (which have the same functions described above) are required: (i) one DFE convolution block 1340 and (ii) one codeword correlator 1330. The number of DFE blocks and correlation blocks required is simplified from 256 to 64. The 64 ICI outputs of blocks 1330 are expanded into 256 ICI outputs from complex operations. Compared to FIG. 12, this architecture calculates the ICI bias for post-CCK codeword correlator correction 1360. Therefore, a codeword correlator to jointly and effectively compute CCK correlations can be effectively implemented using a 64 element fast Walsh transform 1320 and a 1 to 4 expansion 1350. However, each of the 64 post-correlation ICI bias is first calculated using complex convolution 1340 and complex correlation 1330. A 1-to-4 expansion 1330 is then used to generate all 256 post-correlation ICI bias These post-correlation ICI bias are then subtracted from the corresponding 256 correlator outputs of block 1350. To implement this receiver architecture, 64 complex convolution 1340 and complex codeword correlator 1330 need to be performed independently.
In yet another embodiment in FIG. 14 of Webster, for each and every codeword (256 codewords in total), two basic building blocks (which have the same functions described above) are also required: (i) one DFE convolution block 1440 and (ii) one complex codeword correlator 1430. Webster states the fact that the DFE taps can be pre-calculated and pre-stored. Again, the 256 ICI outputs are calculated independently at blocks 1440, and then 256 correlations are found at the outputs of block 1430.
In summary, Webster's architecture requires a chip-based DFE for cancellation of ISI from the previous symbol. To mitigate the ICI distortion due to the present CCK symbol, significant hardware complexity and the execution of large numbers of complex operations (complex multiplications and additions that are required for complex convolution and complex correlation) are needed. As a result, large power consumption, complex hardware, and long processing times will be required to implement the embodiments described in FIGS. 12–14 of Webster.
In U.S. application Ser. No. 10/289,749, filed Nov. 7, 2002 and entitled “Packet-based Multiplication-free CCK Demodulator with a Fast Multipath Interference Cipher”, the present inventors describe a receiver that is provided with an innovative Fast Multipath Interference Cipher (FMIC) to mitigate ICI. As shown in FIG. 2 of Ser. No. 10/289,749, the ICIs for all 256 CCK codewords can be jointly and effectively computed by an innovative FMIC block in a first operation mode (Mode 1). In a separate operation mode (Mode 2), the corresponding ICIs are subtracted from the CCK correlator outputs in the CCK decoder block. This FMIC block implements a Fast Multipath Transform (FMT) having a structure similar to a CCK correlator, which computes the CCK codeword correlations jointly and effectively using the Fast Walsh Transform (FWT). Although the receiver proposed in Ser. No. 10/289,749 can successfully mitigate ICI due to multipath propagations with essentially no additional hardware, it (and in particular, the FMIC) does not mitigate the ISI due to multipath propagation.